?2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6921MR Rev. 1.0.4
11
Electrical Characteristics (Continued)
V
DD
=15 V, T
A
=-40~105 (T
A
=T
J
), unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max. Units
V
CTL-PFC-OFF
Threshold Voltage on FB Pin for
PFC Enable鐳isable
RANGE Pin Internally
Open
1.70
1.75
1.80
V
RANGE Pin Internally
Ground
1.60
1.65
1.70
V
CTL-PFC-ON
Threshold Voltage on FB Pin for
PFC Disable ?Enable
RANGE Pin Internally
Open
1.85
1.90
1.95
V
RANGE Pin Internally
Ground
1.70
1.75
1.80
t
PFC-OFF
PFC Disable Debounce Time
PFC Enable ?
Disable
400
500
600
ms
t
PFC-ON
PFC Enable Debounce Time
PFC Disable ?
Enable
2.0
2.5
3.0
ms
t
STARTER-PWM
Start Timer (Time-Out Timer)
V
FB
V
G
1.85
2.25
2.65
ms
V
FB
V
FB-OLP
22
28
34
祍
PWM Output Section
V
CLAMP
PWM Gate Output Clamping
Voltage
V
DD
=25 V
16.0
17.5
19.0
V
V
OL
PWM Gate Output Voltage Low V
DD
=15 V, I
O
=100 mA
1.5
V
V
OH
PWM Gate Output Voltage High V
DD
=15 V, I
O
=100 mA
8
V
t
R
PWM Gate Output Rising Time
C
L
=3 nF, V
DD
=12 V,
20~80%
80
110
ns
t
F
PWM Gate Output Falling Time
C
L
=3 nF, V
DD
=12 V,
20~80%
40
70
ns
Current Sense Section
t
PD
Delay to Output
150
200
ns
V
LIMIT
The Limit Voltage on CSPWM
Pin for Over Power
Compensation
I
DET
75 礎, T
A
=25癈
0.81
0.84
0.87
V
I
DET
=185 礎, T
A
=25癈
0.69
0.72
0.75
I
DET
=350 礎, T
A
=25癈
0.55
0.58
0.61
I
DET
=550 礎, T
A
=25癈
0.34
0.40
0.46
V
SLOPE
Slope Compensation
(4)
t
ON
=45 祍,
RANGE=Open
0.25
0.30
0.35
V
t
ON
=0 祍
0.05
0.10
0.15
t
ON-BNK
Leading-Edge Blanking Time
300
ns
V
CS-FLOATING
CSPWM Pin Floating V
CSPWM
Clamped High Voltage
CSPWM Pin Floating
4.5
5.0
V
t
CS-H
The Delay Time once CSPWM
Pin Floating
CSPWM Pin Floating
150
祍
Continued on the following page&
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